vphy
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enum  XVphy_LogEvent {
  XVPHY_LOG_EVT_NONE = 1, XVPHY_LOG_EVT_QPLL_EN, XVPHY_LOG_EVT_QPLL_RST, XVPHY_LOG_EVT_QPLL_LOCK,
  XVPHY_LOG_EVT_QPLL_RECONFIG, XVPHY_LOG_EVT_QPLL0_EN, XVPHY_LOG_EVT_QPLL0_RST, XVPHY_LOG_EVT_QPLL0_LOCK,
  XVPHY_LOG_EVT_QPLL0_RECONFIG, XVPHY_LOG_EVT_QPLL1_EN, XVPHY_LOG_EVT_QPLL1_RST, XVPHY_LOG_EVT_QPLL1_LOCK,
  XVPHY_LOG_EVT_QPLL1_RECONFIG, XVPHY_LOG_EVT_PLL0_EN, XVPHY_LOG_EVT_PLL0_RST, XVPHY_LOG_EVT_PLL0_LOCK,
  XVPHY_LOG_EVT_PLL0_RECONFIG, XVPHY_LOG_EVT_PLL1_EN, XVPHY_LOG_EVT_PLL1_RST, XVPHY_LOG_EVT_PLL1_LOCK,
  XVPHY_LOG_EVT_PLL1_RECONFIG, XVPHY_LOG_EVT_CPLL_EN, XVPHY_LOG_EVT_CPLL_RST, XVPHY_LOG_EVT_CPLL_LOCK,
  XVPHY_LOG_EVT_CPLL_RECONFIG, XVPHY_LOG_EVT_TXPLL_EN, XVPHY_LOG_EVT_TXPLL_RST, XVPHY_LOG_EVT_RXPLL_EN,
  XVPHY_LOG_EVT_RXPLL_RST, XVPHY_LOG_EVT_GTRX_RST, XVPHY_LOG_EVT_GTTX_RST, XVPHY_LOG_EVT_VID_TX_RST,
  XVPHY_LOG_EVT_VID_RX_RST, XVPHY_LOG_EVT_TX_ALIGN, XVPHY_LOG_EVT_TX_ALIGN_TMOUT, XVPHY_LOG_EVT_TX_TMR,
  XVPHY_LOG_EVT_RX_TMR, XVPHY_LOG_EVT_GT_RECONFIG, XVPHY_LOG_EVT_GT_TX_RECONFIG, XVPHY_LOG_EVT_GT_RX_RECONFIG,
  XVPHY_LOG_EVT_INIT, XVPHY_LOG_EVT_TXPLL_RECONFIG, XVPHY_LOG_EVT_RXPLL_RECONFIG, XVPHY_LOG_EVT_RXPLL_LOCK,
  XVPHY_LOG_EVT_TXPLL_LOCK, XVPHY_LOG_EVT_TX_RST_DONE, XVPHY_LOG_EVT_RX_RST_DONE, XVPHY_LOG_EVT_TX_FREQ,
  XVPHY_LOG_EVT_RX_FREQ, XVPHY_LOG_EVT_DRU_EN, XVPHY_LOG_EVT_GT_PLL_LAYOUT, XVPHY_LOG_EVT_GT_UNBONDED,
  XVPHY_LOG_EVT_1PPC_ERR, XVPHY_LOG_EVT_PPC_MSMTCH_ERR, XVPHY_LOG_EVT_VDCLK_HIGH_ERR, XVPHY_LOG_EVT_NO_DRU,
  XVPHY_LOG_EVT_GT_QPLL_CFG_ERR, XVPHY_LOG_EVT_GT_CPLL_CFG_ERR, XVPHY_LOG_EVT_VD_NOT_SPRTD_ERR, XVPHY_LOG_EVT_MMCM_ERR,
  XVPHY_LOG_EVT_HDMI20_ERR, XVPHY_LOG_EVT_NO_QPLL_ERR, XVPHY_LOG_EVT_DRU_CLK_ERR, XVPHY_LOG_EVT_USRCLK_ERR,
  XVPHY_LOG_EVT_DUMMY
}
 This typedef enumerates the Video PHY log events. More...
 
enum  XVphy_ErrType {
  XVPHY_ERR_QPLL_CFG = 0x1, XVPHY_ERR_CPLL_CFG = 0x2, XVPHY_ERR_NO_DRU = 0x4, XVPHY_ERR_VD_NOT_SPRTD = 0x8,
  XVPHY_ERR_MMCM_CFG = 0x10, XVPHY_ERR_PLL_LAYOUT = 0x20, XVPHY_ERR_BONDED_DRU = 0x40, XVPHY_ERR_NO_QPLL = 0x80,
  XVPHY_ERR_DRU_CLK = 0x100, XVPHY_ERR_USRCLK = 0x200
}
 This typedef enumerates the possible error conditions. More...
 
enum  XVphy_HdmiTx_Patgen {
  XVPHY_Patgen_Ratio_10 = 0x1, XVPHY_Patgen_Ratio_20 = 0x2, XVPHY_Patgen_Ratio_30 = 0x3, XVPHY_Patgen_Ratio_40 = 0x4,
  XVPHY_Patgen_Ratio_50 = 0x5
}
 This typedef enumerates the Linerate to TMDS Clock ratio for HDMI TX TMDS Clock pattern generator. More...
 

VPHY core registers: General registers.

Address mapping for the Video PHY core.

#define XVPHY_VERSION_REG   0x000
 Version register offset. More...
 
#define XVPHY_BANK_SELECT_REG   0x00C
 Bank select register offset. More...
 
#define XVPHY_REF_CLK_SEL_REG   0x010
 Reference clock select register offset. More...
 
#define XVPHY_PLL_RESET_REG   0x014
 PLL reset register offset. More...
 
#define XVPHY_PLL_LOCK_STATUS_REG   0x018
 PLL lock status register offset. More...
 
#define XVPHY_TX_INIT_REG   0x01C
 TX init register offset. More...
 
#define XVPHY_TX_INIT_STATUS_REG   0x020
 TX init status register offset. More...
 
#define XVPHY_RX_INIT_REG   0x024
 RX init register offset. More...
 
#define XVPHY_RX_INIT_STATUS_REG   0x028
 RX init status register offset. More...
 
#define XVPHY_IBUFDS_GTXX_CTRL_REG   0x02C
 IBUFDS GTXX control register offset. More...
 
#define XVPHY_POWERDOWN_CONTROL_REG   0x030
 Power down control register offset. More...
 
#define XVPHY_LOOPBACK_CONTROL_REG   0x038
 Loopback control register offset. More...
 

VPHY core registers: Dynamic reconfiguration port (DRP) registers.

#define XVPHY_DRP_CONTROL_CH1_REG   0x040
 DRP control channel 1 register offset. More...
 
#define XVPHY_DRP_CONTROL_CH2_REG   0x044
 DRP control channel 2 register offset. More...
 
#define XVPHY_DRP_CONTROL_CH3_REG   0x048
 DRP control channel 3 register offset. More...
 
#define XVPHY_DRP_CONTROL_CH4_REG   0x04C
 DRP control channel 4 register offset. More...
 
#define XVPHY_DRP_STATUS_CH1_REG   0x050
 DRP status channel 1 register offset. More...
 
#define XVPHY_DRP_STATUS_CH2_REG   0x054
 DRP status channel 2 register offset. More...
 
#define XVPHY_DRP_STATUS_CH3_REG   0x058
 DRP status channel 3 register offset. More...
 
#define XVPHY_DRP_STATUS_CH4_REG   0x05C
 DRP status channel 4 register offset. More...
 
#define XVPHY_DRP_CONTROL_COMMON_REG   0x060
 DRP control common register offset. More...
 
#define XVPHY_DRP_STATUS_COMMON_REG   0x064
 DRP status common register offset. More...
 
#define XVPHY_DRP_CONTROL_TXMMCM_REG   0x124
 DRP control TX MMCM register offset. More...
 
#define XVPHY_DRP_STATUS_TXMMCM_REG   0x128
 DRP status TX MMCM register offset. More...
 
#define XVPHY_DRP_CONTROL_RXMMCM_REG   0x144
 DRP control RX MMCM register offset. More...
 
#define XVPHY_DRP_STATUS_RXMMCM_REG   0x148
 DRP status RX MMCM register offset. More...
 

VPHY core registers: CPLL Calibration registers.

#define XVPHY_CPLL_CAL_PERIOD_REG   0x068
 CPLL calibration period register offset. More...
 
#define XVPHY_CPLL_CAL_TOL_REG   0x06C
 CPLL calibration tolerance register offset. More...
 

VPHY core registers: Transmitter function registers.

#define XVPHY_TX_CONTROL_REG   0x070
 TX control register offset. More...
 
#define XVPHY_TX_BUFFER_BYPASS_REG   0x074
 TX buffer bypass register offset. More...
 
#define XVPHY_TX_STATUS_REG   0x078
 TX status register offset. More...
 
#define XVPHY_TX_DRIVER_CH12_REG   0x07C
 TX driver channel 1-2 register offset. More...
 
#define XVPHY_TX_DRIVER_CH34_REG   0x080
 TX driver channel 3-4 register offset. More...
 

VPHY core registers: Receiver function registers.

#define XVPHY_RX_CONTROL_REG   0x100
 RX control register offset. More...
 
#define XVPHY_RX_STATUS_REG   0x104
 RX status register offset. More...
 
#define XVPHY_RX_EQ_CDR_REG   0x108
 RX EQ CDR register offset. More...
 
#define XVPHY_RX_TDLOCK_REG   0x10C
 RX TD lock register offset. More...
 

VPHY core registers: Interrupt registers.

#define XVPHY_ERR_IRQ   0x03C
 Error IRQ register offset. More...
 
#define XVPHY_INTR_EN_REG   0x110
 Interrupt enable register offset. More...
 
#define XVPHY_INTR_DIS_REG   0x114
 Interrupt disable register offset. More...
 
#define XVPHY_INTR_MASK_REG   0x118
 Interrupt mask register offset. More...
 
#define XVPHY_INTR_STS_REG   0x11C
 Interrupt status register offset. More...
 

User clocking registers: MMCM and BUFGGT registers.

#define XVPHY_MMCM_TXUSRCLK_CTRL_REG   0x0120
 MMCM TX user clock control register offset. More...
 
#define XVPHY_MMCM_TXUSRCLK_REG1   0x0124
 MMCM TX user clock register 1 offset. More...
 
#define XVPHY_MMCM_TXUSRCLK_REG2   0x0128
 MMCM TX user clock register 2 offset. More...
 
#define XVPHY_MMCM_TXUSRCLK_REG3   0x012C
 MMCM TX user clock register 3 offset. More...
 
#define XVPHY_MMCM_TXUSRCLK_REG4   0x0130
 MMCM TX user clock register 4 offset. More...
 
#define XVPHY_BUFGGT_TXUSRCLK_REG   0x0134
 BUFGGT TX user clock register offset. More...
 
#define XVPHY_MISC_TXUSRCLK_REG   0x0138
 Misc TX user clock register offset. More...
 
#define XVPHY_MMCM_RXUSRCLK_CTRL_REG   0x0140
 MMCM RX user clock control register offset. More...
 
#define XVPHY_MMCM_RXUSRCLK_REG1   0x0144
 MMCM RX user clock register 1 offset. More...
 
#define XVPHY_MMCM_RXUSRCLK_REG2   0x0148
 MMCM RX user clock register 2 offset. More...
 
#define XVPHY_MMCM_RXUSRCLK_REG3   0x014C
 MMCM RX user clock register 3 offset. More...
 
#define XVPHY_MMCM_RXUSRCLK_REG4   0x0150
 MMCM RX user clock register 4 offset. More...
 
#define XVPHY_BUFGGT_RXUSRCLK_REG   0x0154
 BUFGGT RX user clock register offset. More...
 
#define XVPHY_MISC_RXUSRCLK_REG   0x0158
 Misc RX user clock register offset. More...
 

Clock detector (HDMI) registers.

#define XVPHY_CLKDET_CTRL_REG   0x0200
 Clock detector control register offset. More...
 
#define XVPHY_CLKDET_STAT_REG   0x0204
 Clock detector status register offset. More...
 
#define XVPHY_CLKDET_FREQ_TMR_TO_REG   0x0208
 Clock detector frequency timer timeout register offset. More...
 
#define XVPHY_CLKDET_FREQ_TX_REG   0x020C
 Clock detector TX frequency register offset. More...
 
#define XVPHY_CLKDET_FREQ_RX_REG   0x0210
 Clock detector RX frequency register offset. More...
 
#define XVPHY_CLKDET_TMR_TX_REG   0x0214
 Clock detector TX timer register offset. More...
 
#define XVPHY_CLKDET_TMR_RX_REG   0x0218
 Clock detector RX timer register offset. More...
 
#define XVPHY_CLKDET_FREQ_DRU_REG   0x021C
 Clock detector DRU frequency register offset. More...
 
#define XVPHY_CLKDET_FREQ_TX_RAW_REG   0x0220
 Clock detector RAW TX frequency register offset. More...
 
#define XVPHY_CLKDET_FREQ_RX_RAW_REG   0x0224
 Clock detector RAW RX frequency register offset. More...
 
#define XVPHY_CLKDET_FREQ_DRU_RAW_REG   0x0228
 Clock detector RAW DRU frequency register offset. More...
 

Data recovery unit registers (HDMI).

#define XVPHY_DRU_CTRL_REG   0x0300
 DRU control register offset. More...
 
#define XVPHY_DRU_STAT_REG   0x0304
 DRU status register offset. More...
 
#define XVPHY_DRU_CFREQ_L_REG(Ch)   (0x0308 + (12 * (Ch - 1)))
 DRU center frequency low register offset. More...
 
#define XVPHY_DRU_CFREQ_H_REG(Ch)   (0x030C + (12 * (Ch - 1)))
 DRU center frequency high register offset. More...
 
#define XVPHY_DRU_GAIN_REG(Ch)   (0x0310 + (12 * (Ch - 1)))
 DRU gain register offset. More...
 

TMDS Clock Pattern Generator registers (HDMI).

#define XVPHY_PATGEN_CTRL_REG   0x0340
 Pattern generator control register offset. More...
 

VPHY core masks, shifts, and register values.

#define XVPHY_VERSION_INTER_REV_MASK   0x000000FF
 Internal revision. More...
 
#define XVPHY_VERSION_CORE_PATCH_MASK   0x00000F00
 Core patch details. More...
 
#define XVPHY_VERSION_CORE_PATCH_SHIFT   8
 Shift bits for core patch details. More...
 
#define XVPHY_VERSION_CORE_VER_REV_MASK   0x0000F000
 Core version revision. More...
 
#define XVPHY_VERSION_CORE_VER_REV_SHIFT   12
 Shift bits for core version revision. More...
 
#define XVPHY_VERSION_CORE_VER_MNR_MASK   0x00FF0000
 Core minor version. More...
 
#define XVPHY_VERSION_CORE_VER_MNR_SHIFT   16
 Shift bits for core minor version. More...
 
#define XVPHY_VERSION_CORE_VER_MJR_MASK   0xFF000000
 Core major version. More...
 
#define XVPHY_VERSION_CORE_VER_MJR_SHIFT   24
 Shift bits for core major version. More...
 

0x00C: BANK_SELECT_REG masks and shifts.

#define XVPHY_BANK_SELECT_TX_MASK   0x00F
 TX bank select mask. More...
 
#define XVPHY_BANK_SELECT_RX_MASK   0xF00
 RX bank select mask. More...
 
#define XVPHY_BANK_SELECT_RX_SHIFT   8
 RX bank select shift. More...
 

0x010: REF_CLK_SEL register masks and values.

#define XVPHY_REF_CLK_SEL_QPLL0_MASK   0x0000000F
 QPLL0 refclk select mask. More...
 
#define XVPHY_REF_CLK_SEL_CPLL_MASK   0x000000F0
 CPLL refclk select mask. More...
 
#define XVPHY_REF_CLK_SEL_CPLL_SHIFT   4
 CPLL refclk select shift. More...
 
#define XVPHY_REF_CLK_SEL_QPLL1_MASK   0x00000F00
 QPLL1 refclk select mask. More...
 
#define XVPHY_REF_CLK_SEL_QPLL1_SHIFT   8
 QPLL1 refclk select shift. More...
 
#define XVPHY_REF_CLK_SEL_XPLL_GTREFCLK0   1
 GTREFCLK0 select value. More...
 
#define XVPHY_REF_CLK_SEL_XPLL_GTREFCLK1   2
 GTREFCLK1 select value. More...
 
#define XVPHY_REF_CLK_SEL_XPLL_GTNORTHREFCLK0   3
 GTNORTHREFCLK0 select value. More...
 
#define XVPHY_REF_CLK_SEL_XPLL_GTNORTHREFCLK1   4
 GTNORTHREFCLK1 select value. More...
 
#define XVPHY_REF_CLK_SEL_XPLL_GTSOUTHREFCLK0   5
 GTSOUTHREFCLK0 select value. More...
 
#define XVPHY_REF_CLK_SEL_XPLL_GTSOUTHREFCLK1   6
 GTSOUTHREFCLK1 select value. More...
 
#define XVPHY_REF_CLK_SEL_XPLL_GTEASTREFCLK0   3
 GTEASTREFCLK0 select value. More...
 
#define XVPHY_REF_CLK_SEL_XPLL_GTEASTREFCLK1   4
 GTEASTREFCLK1 select value. More...
 
#define XVPHY_REF_CLK_SEL_XPLL_GTWESTREFCLK0   5
 GTWESTREFCLK0 select value. More...
 
#define XVPHY_REF_CLK_SEL_XPLL_GTWESTREFCLK1   6
 GTWESTREFCLK1 select value. More...
 
#define XVPHY_REF_CLK_SEL_XPLL_GTGREFCLK   7
 GTGREFCLK select value. More...
 
#define XVPHY_REF_CLK_SEL_SYSCLKSEL_MASK   0x0F000000
 SYSCLKSEL mask. More...
 
#define XVPHY_REF_CLK_SEL_SYSCLKSEL_SHIFT   24
 SYSCLKSEL shift. More...
 
#define XVPHY_REF_CLK_SEL_XXSYSCLKSEL_DATA_PLL0   0
 SYSGLKSEL data PLL0 value. More...
 
#define XVPHY_REF_CLK_SEL_XXSYSCLKSEL_DATA_PLL1   1
 SYSCLKSEL data PLL1 value. More...
 
#define XVPHY_REF_CLK_SEL_XXSYSCLKSEL_DATA_CPLL   0
 SYSCLKSEL data CPLL value. More...
 
#define XVPHY_REF_CLK_SEL_XXSYSCLKSEL_DATA_QPLL   1
 SYSCLKSEL data QPLL value. More...
 
#define XVPHY_REF_CLK_SEL_XXSYSCLKSEL_DATA_QPLL0   3
 SYSCLKSEL data QPLL0 value. More...
 
#define XVPHY_REF_CLK_SEL_XXSYSCLKSEL_DATA_QPLL1   2
 SYSCLKSEL data QPLL1 value. More...
 
#define XVPHY_REF_CLK_SEL_XXSYSCLKSEL_OUT_CH   0
 SYSCLKSEL out channel value. More...
 
#define XVPHY_REF_CLK_SEL_XXSYSCLKSEL_OUT_CMN   1
 SYSCLKSEL out common value. More...
 
#define XVPHY_REF_CLK_SEL_XXSYSCLKSEL_OUT_CMN0   2
 SYSCLKSEL out CMN0 value. More...
 
#define XVPHY_REF_CLK_SEL_XXSYSCLKSEL_OUT_CMN1   3
 SYSCLKSEL out CMN1 value. More...
 
#define XVPHY_REF_CLK_SEL_RXSYSCLKSEL_OUT_MASK(G)
 RX SYSCLKSEL out mask based on GT type. More...
 
#define XVPHY_REF_CLK_SEL_TXSYSCLKSEL_OUT_MASK(G)
 TX SYSCLKSEL out mask based on GT type. More...
 
#define XVPHY_REF_CLK_SEL_RXSYSCLKSEL_DATA_MASK(G)
 RX SYSCLKSEL data mask based on GT type. More...
 
#define XVPHY_REF_CLK_SEL_TXSYSCLKSEL_DATA_MASK(G)
 TX SYSCLKSEL data mask based on GT type. More...
 
#define XVPHY_REF_CLK_SEL_RXSYSCLKSEL_OUT_SHIFT(G)
 RX SYSCLKSEL out shift based on GT type. More...
 
#define XVPHY_REF_CLK_SEL_TXSYSCLKSEL_OUT_SHIFT(G)
 TX SYSCLKSEL out shift based on GT type. More...
 
#define XVPHY_REF_CLK_SEL_RXSYSCLKSEL_DATA_SHIFT(G)
 RX SYSCLKSEL data shift based on GT type. More...
 
#define XVPHY_REF_CLK_SEL_TXSYSCLKSEL_DATA_SHIFT(G)
 TX SYSCLKSEL data shift based on GT type. More...
 

0x014: PLL_RESET register masks.

#define XVPHY_PLL_RESET_CPLL_MASK   0x1
 CPLL reset mask. More...
 
#define XVPHY_PLL_RESET_QPLL0_MASK   0x2
 QPLL0 reset mask. More...
 
#define XVPHY_PLL_RESET_QPLL1_MASK   0x4
 QPLL1 reset mask. More...
 

0x018: PLL_LOCK_STATUS register masks.

#define XVPHY_PLL_LOCK_STATUS_CPLL_MASK(Ch)   (0x01 << (Ch - 1))
 CPLL lock status mask for channel. More...
 
#define XVPHY_PLL_LOCK_STATUS_QPLL0_MASK   0x10
 QPLL0 lock status mask. More...
 
#define XVPHY_PLL_LOCK_STATUS_QPLL1_MASK   0x20
 QPLL1 lock status mask. More...
 
#define XVPHY_PLL_LOCK_STATUS_CPLL_ALL_MASK
 CPLL lock status mask for all channels. More...
 
#define XVPHY_PLL_LOCK_STATUS_CPLL_HDMI_MASK
 CPLL lock status mask for HDMI channels. More...
 

0x01C, 0x024: TX_INIT, RX_INIT register masks.

#define XVPHY_TXRX_INIT_GTRESET_MASK(Ch)   (0x01 << (8 * (Ch - 1)))
 GT reset mask for channel. More...
 
#define XVPHY_TXRX_INIT_PMARESET_MASK(Ch)   (0x02 << (8 * (Ch - 1)))
 PMA reset mask for channel. More...
 
#define XVPHY_TXRX_INIT_PCSRESET_MASK(Ch)   (0x04 << (8 * (Ch - 1)))
 PCS reset mask for channel. More...
 
#define XVPHY_TX_INIT_USERRDY_MASK(Ch)   (0x08 << (8 * (Ch - 1)))
 TX user ready mask for channel. More...
 
#define XVPHY_RX_INIT_USERRDY_MASK(Ch)   (0x40 << (8 * (Ch - 1)))
 RX user ready mask for channel. More...
 
#define XVPHY_TXRX_INIT_PLLGTRESET_MASK(Ch)   (0x80 << (8 * (Ch - 1)))
 PLL GT reset mask for channel. More...
 
#define XVPHY_TXRX_INIT_GTRESET_ALL_MASK
 GT reset mask for all channels. More...
 
#define XVPHY_TX_INIT_USERRDY_ALL_MASK
 TX user ready mask for all channels. More...
 
#define XVPHY_RX_INIT_USERRDY_ALL_MASK
 RX user ready mask for all channels. More...
 
#define XVPHY_TXRX_INIT_PLLGTRESET_ALL_MASK
 PLL GT reset mask for all channels. More...
 

0x020, 0x028: TX_STATUS, RX_STATUS register masks.

#define XVPHY_TXRX_INIT_STATUS_RESETDONE_MASK(Ch)   (0x01 << (8 * (Ch - 1)))
 Reset done mask for channel. More...
 
#define XVPHY_TXRX_INIT_STATUS_PMARESETDONE_MASK(Ch)   (0x02 << (8 * (Ch - 1)))
 PMA reset done mask for channel. More...
 
#define XVPHY_TXRX_INIT_STATUS_POWERGOOD_MASK(Ch)   (0x04 << (8 * (Ch - 1)))
 Power good mask for channel. More...
 
#define XVPHY_TXRX_INIT_STATUS_RESETDONE_ALL_MASK
 Reset done mask for all channels. More...
 
#define XVPHY_TXRX_INIT_STATUS_PMARESETDONE_ALL_MASK
 PMA reset done mask for all channels. More...
 

0x02C: IBUFDS_GTXX_CTRL register masks.

#define XVPHY_IBUFDS_GTXX_CTRL_GTREFCLK0_CEB_MASK   0x1
 GTREFCLK0 CEB mask. More...
 
#define XVPHY_IBUFDS_GTXX_CTRL_GTREFCLK1_CEB_MASK   0x2
 GTREFCLK1 CEB mask. More...
 

0x030: POWERDOWN_CONTROL register masks.

#define XVPHY_POWERDOWN_CONTROL_CPLLPD_MASK(Ch)   (0x01 << (8 * (Ch - 1)))
 CPLL power down mask for channel. More...
 
#define XVPHY_POWERDOWN_CONTROL_QPLL0PD_MASK(Ch)   (0x02 << (8 * (Ch - 1)))
 QPLL0 power down mask for channel. More...
 
#define XVPHY_POWERDOWN_CONTROL_QPLL1PD_MASK(Ch)   (0x04 << (8 * (Ch - 1)))
 QPLL1 power down mask for channel. More...
 
#define XVPHY_POWERDOWN_CONTROL_RXPD_MASK(Ch)   (0x18 << (8 * (Ch - 1)))
 RX power down mask for channel. More...
 
#define XVPHY_POWERDOWN_CONTROL_RXPD_SHIFT(Ch)   (3 + (8 * (Ch - 1)))
 RX power down shift for channel. More...
 
#define XVPHY_POWERDOWN_CONTROL_TXPD_MASK(Ch)   (0x60 << (8 * (Ch - 1)))
 TX power down mask for channel. More...
 
#define XVPHY_POWERDOWN_CONTROL_TXPD_SHIFT(Ch)   (5 + (8 * (Ch - 1)))
 TX power down shift for channel. More...
 

0x038: LOOPBACK_CONTROL register masks.

#define XVPHY_LOOPBACK_CONTROL_CH_MASK(Ch)   (0x03 << (8 * (Ch - 1)))
 Loopback control mask for channel. More...
 
#define XVPHY_LOOPBACK_CONTROL_CH_SHIFT(Ch)   (8 * (Ch - 1))
 Loopback control shift for channel. More...
 

Macro Definition Documentation

#define XVPHY_BANK_SELECT_REG   0x00C

Bank select register offset.

#define XVPHY_BANK_SELECT_RX_MASK   0xF00

RX bank select mask.

#define XVPHY_BANK_SELECT_RX_SHIFT   8

RX bank select shift.

#define XVPHY_BANK_SELECT_TX_MASK   0x00F

TX bank select mask.

#define XVPHY_BUFGGT_RXUSRCLK_REG   0x0154

BUFGGT RX user clock register offset.

Referenced by XVphy_SetBufgGtDiv().

#define XVPHY_BUFGGT_TXUSRCLK_REG   0x0134

BUFGGT TX user clock register offset.

Referenced by XVphy_SetBufgGtDiv().

#define XVPHY_CLKDET_CTRL_REG   0x0200

Clock detector control register offset.

#define XVPHY_CLKDET_FREQ_DRU_RAW_REG   0x0228

Clock detector RAW DRU frequency register offset.

#define XVPHY_CLKDET_FREQ_DRU_REG   0x021C

Clock detector DRU frequency register offset.

#define XVPHY_CLKDET_FREQ_RX_RAW_REG   0x0224

Clock detector RAW RX frequency register offset.

#define XVPHY_CLKDET_FREQ_RX_REG   0x0210

Clock detector RX frequency register offset.

#define XVPHY_CLKDET_FREQ_TMR_TO_REG   0x0208

Clock detector frequency timer timeout register offset.

#define XVPHY_CLKDET_FREQ_TX_RAW_REG   0x0220

Clock detector RAW TX frequency register offset.

#define XVPHY_CLKDET_FREQ_TX_REG   0x020C

Clock detector TX frequency register offset.

#define XVPHY_CLKDET_STAT_REG   0x0204

Clock detector status register offset.

#define XVPHY_CLKDET_TMR_RX_REG   0x0218

Clock detector RX timer register offset.

#define XVPHY_CLKDET_TMR_TX_REG   0x0214

Clock detector TX timer register offset.

#define XVPHY_CPLL_CAL_PERIOD_REG   0x068

CPLL calibration period register offset.

#define XVPHY_CPLL_CAL_TOL_REG   0x06C

CPLL calibration tolerance register offset.

#define XVPHY_DRP_CONTROL_CH1_REG   0x040

DRP control channel 1 register offset.

#define XVPHY_DRP_CONTROL_CH2_REG   0x044

DRP control channel 2 register offset.

#define XVPHY_DRP_CONTROL_CH3_REG   0x048

DRP control channel 3 register offset.

#define XVPHY_DRP_CONTROL_CH4_REG   0x04C

DRP control channel 4 register offset.

#define XVPHY_DRP_CONTROL_COMMON_REG   0x060

DRP control common register offset.

#define XVPHY_DRP_CONTROL_RXMMCM_REG   0x144

DRP control RX MMCM register offset.

#define XVPHY_DRP_CONTROL_TXMMCM_REG   0x124

DRP control TX MMCM register offset.

#define XVPHY_DRP_STATUS_CH1_REG   0x050

DRP status channel 1 register offset.

#define XVPHY_DRP_STATUS_CH2_REG   0x054

DRP status channel 2 register offset.

#define XVPHY_DRP_STATUS_CH3_REG   0x058

DRP status channel 3 register offset.

#define XVPHY_DRP_STATUS_CH4_REG   0x05C

DRP status channel 4 register offset.

#define XVPHY_DRP_STATUS_COMMON_REG   0x064

DRP status common register offset.

#define XVPHY_DRP_STATUS_RXMMCM_REG   0x148

DRP status RX MMCM register offset.

#define XVPHY_DRP_STATUS_TXMMCM_REG   0x128

DRP status TX MMCM register offset.

#define XVPHY_DRU_CFREQ_H_REG (   Ch)    (0x030C + (12 * (Ch - 1)))

DRU center frequency high register offset.

#define XVPHY_DRU_CFREQ_L_REG (   Ch)    (0x0308 + (12 * (Ch - 1)))

DRU center frequency low register offset.

#define XVPHY_DRU_CTRL_REG   0x0300

DRU control register offset.

#define XVPHY_DRU_GAIN_REG (   Ch)    (0x0310 + (12 * (Ch - 1)))

DRU gain register offset.

#define XVPHY_DRU_STAT_REG   0x0304

DRU status register offset.

#define XVPHY_ERR_IRQ   0x03C

Error IRQ register offset.

Referenced by XVphy_CfgErrIntr().

#define XVPHY_IBUFDS_GTXX_CTRL_GTREFCLK0_CEB_MASK   0x1

GTREFCLK0 CEB mask.

Referenced by XVphy_IBufDsEnable().

#define XVPHY_IBUFDS_GTXX_CTRL_GTREFCLK1_CEB_MASK   0x2

GTREFCLK1 CEB mask.

Referenced by XVphy_IBufDsEnable().

#define XVPHY_IBUFDS_GTXX_CTRL_REG   0x02C

IBUFDS GTXX control register offset.

Referenced by XVphy_IBufDsEnable().

#define XVPHY_INTR_DIS_REG   0x114

Interrupt disable register offset.

Referenced by XVphy_IntrDisable().

#define XVPHY_INTR_EN_REG   0x110

Interrupt enable register offset.

Referenced by XVphy_IntrEnable().

#define XVPHY_INTR_MASK_REG   0x118

Interrupt mask register offset.

#define XVPHY_INTR_STS_REG   0x11C

Interrupt status register offset.

Referenced by XVphy_InterruptHandler().

#define XVPHY_LOOPBACK_CONTROL_CH_MASK (   Ch)    (0x03 << (8 * (Ch - 1)))

Loopback control mask for channel.

#define XVPHY_LOOPBACK_CONTROL_CH_SHIFT (   Ch)    (8 * (Ch - 1))

Loopback control shift for channel.

#define XVPHY_LOOPBACK_CONTROL_REG   0x038

Loopback control register offset.

#define XVPHY_MISC_RXUSRCLK_REG   0x0158

Misc RX user clock register offset.

Referenced by XVphy_Clkout1OBufTdsEnable(), and XVphy_IBufDsEnable().

#define XVPHY_MISC_TXUSRCLK_REG   0x0138

Misc TX user clock register offset.

Referenced by XVphy_Clkout1OBufTdsEnable(), and XVphy_IBufDsEnable().

#define XVPHY_MMCM_RXUSRCLK_CTRL_REG   0x0140

MMCM RX user clock control register offset.

Referenced by XVphy_MmcmLocked(), XVphy_MmcmLockedMaskEnable(), XVphy_MmcmPowerDown(), and XVphy_MmcmReset().

#define XVPHY_MMCM_RXUSRCLK_REG1   0x0144

MMCM RX user clock register 1 offset.

#define XVPHY_MMCM_RXUSRCLK_REG2   0x0148

MMCM RX user clock register 2 offset.

#define XVPHY_MMCM_RXUSRCLK_REG3   0x014C

MMCM RX user clock register 3 offset.

#define XVPHY_MMCM_RXUSRCLK_REG4   0x0150

MMCM RX user clock register 4 offset.

#define XVPHY_MMCM_TXUSRCLK_CTRL_REG   0x0120

MMCM TX user clock control register offset.

Referenced by XVphy_MmcmLocked(), XVphy_MmcmLockedMaskEnable(), XVphy_MmcmPowerDown(), and XVphy_MmcmReset().

#define XVPHY_MMCM_TXUSRCLK_REG1   0x0124

MMCM TX user clock register 1 offset.

#define XVPHY_MMCM_TXUSRCLK_REG2   0x0128

MMCM TX user clock register 2 offset.

#define XVPHY_MMCM_TXUSRCLK_REG3   0x012C

MMCM TX user clock register 3 offset.

#define XVPHY_MMCM_TXUSRCLK_REG4   0x0130

MMCM TX user clock register 4 offset.

#define XVPHY_PATGEN_CTRL_REG   0x0340

Pattern generator control register offset.

#define XVPHY_PLL_LOCK_STATUS_CPLL_ALL_MASK
Value:
(XVPHY_PLL_LOCK_STATUS_CPLL_MASK(XVPHY_CHANNEL_ID_CH1) | \
XVPHY_PLL_LOCK_STATUS_CPLL_MASK(XVPHY_CHANNEL_ID_CH2) | \
XVPHY_PLL_LOCK_STATUS_CPLL_MASK(XVPHY_CHANNEL_ID_CH3) | \
XVPHY_PLL_LOCK_STATUS_CPLL_MASK(XVPHY_CHANNEL_ID_CH4))
XVPHY_PLL_LOCK_STATUS_CPLL_MASK
#define XVPHY_PLL_LOCK_STATUS_CPLL_MASK(Ch)
CPLL lock status mask for channel.
Definition: xvphy_hw.h:301

CPLL lock status mask for all channels.

Referenced by XVphy_IsPllLocked().

#define XVPHY_PLL_LOCK_STATUS_CPLL_HDMI_MASK
Value:
(XVPHY_PLL_LOCK_STATUS_CPLL_MASK(XVPHY_CHANNEL_ID_CH1) | \
XVPHY_PLL_LOCK_STATUS_CPLL_MASK(XVPHY_CHANNEL_ID_CH2) | \
XVPHY_PLL_LOCK_STATUS_CPLL_MASK(XVPHY_CHANNEL_ID_CH3))
XVPHY_PLL_LOCK_STATUS_CPLL_MASK
#define XVPHY_PLL_LOCK_STATUS_CPLL_MASK(Ch)
CPLL lock status mask for channel.
Definition: xvphy_hw.h:301

CPLL lock status mask for HDMI channels.

Referenced by XVphy_IsPllLocked().

#define XVPHY_PLL_LOCK_STATUS_CPLL_MASK (   Ch)    (0x01 << (Ch - 1))

CPLL lock status mask for channel.

Referenced by XVphy_IsPllLocked().

#define XVPHY_PLL_LOCK_STATUS_QPLL0_MASK   0x10

QPLL0 lock status mask.

Referenced by XVphy_IsPllLocked().

#define XVPHY_PLL_LOCK_STATUS_QPLL1_MASK   0x20

QPLL1 lock status mask.

Referenced by XVphy_IsPllLocked().

#define XVPHY_PLL_LOCK_STATUS_REG   0x018

PLL lock status register offset.

Referenced by XVphy_IsPllLocked().

#define XVPHY_PLL_RESET_CPLL_MASK   0x1

CPLL reset mask.

#define XVPHY_PLL_RESET_QPLL0_MASK   0x2

QPLL0 reset mask.

#define XVPHY_PLL_RESET_QPLL1_MASK   0x4

QPLL1 reset mask.

#define XVPHY_PLL_RESET_REG   0x014

PLL reset register offset.

#define XVPHY_POWERDOWN_CONTROL_CPLLPD_MASK (   Ch)    (0x01 << (8 * (Ch - 1)))

CPLL power down mask for channel.

Referenced by XVphy_PowerDownGtPll().

#define XVPHY_POWERDOWN_CONTROL_QPLL0PD_MASK (   Ch)    (0x02 << (8 * (Ch - 1)))

QPLL0 power down mask for channel.

Referenced by XVphy_PowerDownGtPll().

#define XVPHY_POWERDOWN_CONTROL_QPLL1PD_MASK (   Ch)    (0x04 << (8 * (Ch - 1)))

QPLL1 power down mask for channel.

Referenced by XVphy_PowerDownGtPll().

#define XVPHY_POWERDOWN_CONTROL_REG   0x030

Power down control register offset.

Referenced by XVphy_PowerDownGtPll().

#define XVPHY_POWERDOWN_CONTROL_RXPD_MASK (   Ch)    (0x18 << (8 * (Ch - 1)))

RX power down mask for channel.

#define XVPHY_POWERDOWN_CONTROL_RXPD_SHIFT (   Ch)    (3 + (8 * (Ch - 1)))

RX power down shift for channel.

#define XVPHY_POWERDOWN_CONTROL_TXPD_MASK (   Ch)    (0x60 << (8 * (Ch - 1)))

TX power down mask for channel.

#define XVPHY_POWERDOWN_CONTROL_TXPD_SHIFT (   Ch)    (5 + (8 * (Ch - 1)))

TX power down shift for channel.

#define XVPHY_REF_CLK_SEL_CPLL_MASK   0x000000F0

CPLL refclk select mask.

Referenced by XVphy_WriteCfgRefClkSelReg().

#define XVPHY_REF_CLK_SEL_CPLL_SHIFT   4

CPLL refclk select shift.

Referenced by XVphy_WriteCfgRefClkSelReg().

#define XVPHY_REF_CLK_SEL_QPLL0_MASK   0x0000000F

QPLL0 refclk select mask.

Referenced by XVphy_WriteCfgRefClkSelReg().

#define XVPHY_REF_CLK_SEL_QPLL1_MASK   0x00000F00

QPLL1 refclk select mask.

Referenced by XVphy_WriteCfgRefClkSelReg().

#define XVPHY_REF_CLK_SEL_QPLL1_SHIFT   8

QPLL1 refclk select shift.

Referenced by XVphy_WriteCfgRefClkSelReg().

#define XVPHY_REF_CLK_SEL_REG   0x010

Reference clock select register offset.

Referenced by XVphy_GetSysClkDataSel(), XVphy_GetSysClkOutSel(), and XVphy_WriteCfgRefClkSelReg().

#define XVPHY_REF_CLK_SEL_RXSYSCLKSEL_DATA_MASK (   G)
Value:
((((G) == XVPHY_GT_TYPE_GTHE3) || \
((G) == XVPHY_GT_TYPE_GTHE4) || \
((G) == XVPHY_GT_TYPE_GTYE4)) ? 0x30000000 : 0x01000000)

RX SYSCLKSEL data mask based on GT type.

Referenced by XVphy_GetSysClkDataSel(), and XVphy_WriteCfgRefClkSelReg().

#define XVPHY_REF_CLK_SEL_RXSYSCLKSEL_DATA_SHIFT (   G)
Value:
((((G) == XVPHY_GT_TYPE_GTHE3) || \
((G) == XVPHY_GT_TYPE_GTHE4) || \
((G) == XVPHY_GT_TYPE_GTYE4)) ? 28 : 24)

RX SYSCLKSEL data shift based on GT type.

Referenced by XVphy_GetSysClkDataSel(), and XVphy_WriteCfgRefClkSelReg().

#define XVPHY_REF_CLK_SEL_RXSYSCLKSEL_OUT_MASK (   G)
Value:
((((G) == XVPHY_GT_TYPE_GTHE3) || \
((G) == XVPHY_GT_TYPE_GTHE4) || \
((G) == XVPHY_GT_TYPE_GTYE4)) ? 0x03000000 : 0x02000000)

RX SYSCLKSEL out mask based on GT type.

Referenced by XVphy_GetSysClkOutSel(), and XVphy_WriteCfgRefClkSelReg().

#define XVPHY_REF_CLK_SEL_RXSYSCLKSEL_OUT_SHIFT (   G)
Value:
((((G) == XVPHY_GT_TYPE_GTHE3) || \
((G) == XVPHY_GT_TYPE_GTHE4) || \
((G) == XVPHY_GT_TYPE_GTYE4)) ? 24 : 25)

RX SYSCLKSEL out shift based on GT type.

Referenced by XVphy_GetSysClkOutSel(), and XVphy_WriteCfgRefClkSelReg().

#define XVPHY_REF_CLK_SEL_SYSCLKSEL_MASK   0x0F000000

SYSCLKSEL mask.

Referenced by XVphy_WriteCfgRefClkSelReg().

#define XVPHY_REF_CLK_SEL_SYSCLKSEL_SHIFT   24

SYSCLKSEL shift.

#define XVPHY_REF_CLK_SEL_TXSYSCLKSEL_DATA_MASK (   G)
Value:
((((G) == XVPHY_GT_TYPE_GTHE3) || \
((G) == XVPHY_GT_TYPE_GTHE4) || \
((G) == XVPHY_GT_TYPE_GTYE4)) ? 0xC0000000 : 0x04000000)

TX SYSCLKSEL data mask based on GT type.

Referenced by XVphy_GetSysClkDataSel(), and XVphy_WriteCfgRefClkSelReg().

#define XVPHY_REF_CLK_SEL_TXSYSCLKSEL_DATA_SHIFT (   G)
Value:
((((G) == XVPHY_GT_TYPE_GTHE3) || \
((G) == XVPHY_GT_TYPE_GTHE4) || \
((G) == XVPHY_GT_TYPE_GTYE4)) ? 30 : 26)

TX SYSCLKSEL data shift based on GT type.

Referenced by XVphy_GetSysClkDataSel(), and XVphy_WriteCfgRefClkSelReg().

#define XVPHY_REF_CLK_SEL_TXSYSCLKSEL_OUT_MASK (   G)
Value:
((((G) == XVPHY_GT_TYPE_GTHE3) || \
((G) == XVPHY_GT_TYPE_GTHE4) || \
((G) == XVPHY_GT_TYPE_GTYE4)) ? 0x0C000000 : 0x08000000)

TX SYSCLKSEL out mask based on GT type.

Referenced by XVphy_GetSysClkOutSel(), and XVphy_WriteCfgRefClkSelReg().

#define XVPHY_REF_CLK_SEL_TXSYSCLKSEL_OUT_SHIFT (   G)
Value:
((((G) == XVPHY_GT_TYPE_GTHE3) || \
((G) == XVPHY_GT_TYPE_GTHE4) || \
((G) == XVPHY_GT_TYPE_GTYE4)) ? 26 : 27)

TX SYSCLKSEL out shift based on GT type.

Referenced by XVphy_GetSysClkOutSel(), and XVphy_WriteCfgRefClkSelReg().

#define XVPHY_REF_CLK_SEL_XPLL_GTEASTREFCLK0   3

GTEASTREFCLK0 select value.

#define XVPHY_REF_CLK_SEL_XPLL_GTEASTREFCLK1   4

GTEASTREFCLK1 select value.

#define XVPHY_REF_CLK_SEL_XPLL_GTGREFCLK   7

GTGREFCLK select value.

#define XVPHY_REF_CLK_SEL_XPLL_GTNORTHREFCLK0   3

GTNORTHREFCLK0 select value.

#define XVPHY_REF_CLK_SEL_XPLL_GTNORTHREFCLK1   4

GTNORTHREFCLK1 select value.

#define XVPHY_REF_CLK_SEL_XPLL_GTREFCLK0   1

GTREFCLK0 select value.

#define XVPHY_REF_CLK_SEL_XPLL_GTREFCLK1   2

GTREFCLK1 select value.

#define XVPHY_REF_CLK_SEL_XPLL_GTSOUTHREFCLK0   5

GTSOUTHREFCLK0 select value.

#define XVPHY_REF_CLK_SEL_XPLL_GTSOUTHREFCLK1   6

GTSOUTHREFCLK1 select value.

#define XVPHY_REF_CLK_SEL_XPLL_GTWESTREFCLK0   5

GTWESTREFCLK0 select value.

#define XVPHY_REF_CLK_SEL_XPLL_GTWESTREFCLK1   6

GTWESTREFCLK1 select value.

#define XVPHY_REF_CLK_SEL_XXSYSCLKSEL_DATA_CPLL   0

SYSCLKSEL data CPLL value.

#define XVPHY_REF_CLK_SEL_XXSYSCLKSEL_DATA_PLL0   0

SYSGLKSEL data PLL0 value.

#define XVPHY_REF_CLK_SEL_XXSYSCLKSEL_DATA_PLL1   1

SYSCLKSEL data PLL1 value.

#define XVPHY_REF_CLK_SEL_XXSYSCLKSEL_DATA_QPLL   1

SYSCLKSEL data QPLL value.

#define XVPHY_REF_CLK_SEL_XXSYSCLKSEL_DATA_QPLL0   3

SYSCLKSEL data QPLL0 value.

#define XVPHY_REF_CLK_SEL_XXSYSCLKSEL_DATA_QPLL1   2

SYSCLKSEL data QPLL1 value.

#define XVPHY_REF_CLK_SEL_XXSYSCLKSEL_OUT_CH   0

SYSCLKSEL out channel value.

#define XVPHY_REF_CLK_SEL_XXSYSCLKSEL_OUT_CMN   1

SYSCLKSEL out common value.

#define XVPHY_REF_CLK_SEL_XXSYSCLKSEL_OUT_CMN0   2

SYSCLKSEL out CMN0 value.

#define XVPHY_REF_CLK_SEL_XXSYSCLKSEL_OUT_CMN1   3

SYSCLKSEL out CMN1 value.

#define XVPHY_RX_CONTROL_REG   0x100

RX control register offset.

Referenced by XVphy_SetPolarity(), and XVphy_SetPrbsSel().

#define XVPHY_RX_EQ_CDR_REG   0x108

RX EQ CDR register offset.

Referenced by XVphy_SetRxLpm().

#define XVPHY_RX_INIT_REG   0x024

RX init register offset.

Referenced by XVphy_GtUserRdyEnable(), XVphy_ResetGtPll(), and XVphy_ResetGtTxRx().

#define XVPHY_RX_INIT_STATUS_REG   0x028

RX init status register offset.

#define XVPHY_RX_INIT_USERRDY_ALL_MASK
Value:
(XVPHY_RX_INIT_USERRDY_MASK(XVPHY_CHANNEL_ID_CH1) | \
XVPHY_RX_INIT_USERRDY_MASK(XVPHY_CHANNEL_ID_CH2) | \
XVPHY_RX_INIT_USERRDY_MASK(XVPHY_CHANNEL_ID_CH3) | \
XVPHY_RX_INIT_USERRDY_MASK(XVPHY_CHANNEL_ID_CH4))
XVPHY_RX_INIT_USERRDY_MASK
#define XVPHY_RX_INIT_USERRDY_MASK(Ch)
RX user ready mask for channel.
Definition: xvphy_hw.h:334

RX user ready mask for all channels.

Referenced by XVphy_GtUserRdyEnable().

#define XVPHY_RX_INIT_USERRDY_MASK (   Ch)    (0x40 << (8 * (Ch - 1)))

RX user ready mask for channel.

Referenced by XVphy_GtUserRdyEnable().

#define XVPHY_RX_STATUS_REG   0x104

RX status register offset.

#define XVPHY_RX_TDLOCK_REG   0x10C

RX TD lock register offset.

#define XVPHY_TX_BUFFER_BYPASS_REG   0x074

TX buffer bypass register offset.

#define XVPHY_TX_CONTROL_REG   0x070

TX control register offset.

Referenced by XVphy_SetPolarity(), XVphy_SetPrbsSel(), and XVphy_TxPrbsForceError().

#define XVPHY_TX_DRIVER_CH12_REG   0x07C

TX driver channel 1-2 register offset.

Referenced by XVphy_SetTxPostCursor(), XVphy_SetTxPreEmphasis(), and XVphy_SetTxVoltageSwing().

#define XVPHY_TX_DRIVER_CH34_REG   0x080

TX driver channel 3-4 register offset.

Referenced by XVphy_SetTxPostCursor(), XVphy_SetTxPreEmphasis(), and XVphy_SetTxVoltageSwing().

#define XVPHY_TX_INIT_REG   0x01C

TX init register offset.

Referenced by XVphy_GtUserRdyEnable(), XVphy_ResetGtPll(), and XVphy_ResetGtTxRx().

#define XVPHY_TX_INIT_STATUS_REG   0x020

TX init status register offset.

#define XVPHY_TX_INIT_USERRDY_ALL_MASK
Value:
(XVPHY_TX_INIT_USERRDY_MASK(XVPHY_CHANNEL_ID_CH1) | \
XVPHY_TX_INIT_USERRDY_MASK(XVPHY_CHANNEL_ID_CH2) | \
XVPHY_TX_INIT_USERRDY_MASK(XVPHY_CHANNEL_ID_CH3) | \
XVPHY_TX_INIT_USERRDY_MASK(XVPHY_CHANNEL_ID_CH4))
XVPHY_TX_INIT_USERRDY_MASK
#define XVPHY_TX_INIT_USERRDY_MASK(Ch)
TX user ready mask for channel.
Definition: xvphy_hw.h:331

TX user ready mask for all channels.

Referenced by XVphy_GtUserRdyEnable().

#define XVPHY_TX_INIT_USERRDY_MASK (   Ch)    (0x08 << (8 * (Ch - 1)))

TX user ready mask for channel.

Referenced by XVphy_GtUserRdyEnable().

#define XVPHY_TX_STATUS_REG   0x078

TX status register offset.

#define XVPHY_TXRX_INIT_GTRESET_ALL_MASK
Value:
(XVPHY_TXRX_INIT_GTRESET_MASK(XVPHY_CHANNEL_ID_CH1) | \
XVPHY_TXRX_INIT_GTRESET_MASK(XVPHY_CHANNEL_ID_CH2) | \
XVPHY_TXRX_INIT_GTRESET_MASK(XVPHY_CHANNEL_ID_CH3) | \
XVPHY_TXRX_INIT_GTRESET_MASK(XVPHY_CHANNEL_ID_CH4))
XVPHY_TXRX_INIT_GTRESET_MASK
#define XVPHY_TXRX_INIT_GTRESET_MASK(Ch)
GT reset mask for channel.
Definition: xvphy_hw.h:322

GT reset mask for all channels.

Referenced by XVphy_ResetGtTxRx().

#define XVPHY_TXRX_INIT_GTRESET_MASK (   Ch)    (0x01 << (8 * (Ch - 1)))

GT reset mask for channel.

Referenced by XVphy_ResetGtTxRx().

#define XVPHY_TXRX_INIT_PCSRESET_MASK (   Ch)    (0x04 << (8 * (Ch - 1)))

PCS reset mask for channel.

#define XVPHY_TXRX_INIT_PLLGTRESET_ALL_MASK
Value:
(XVPHY_TXRX_INIT_PLLGTRESET_MASK(XVPHY_CHANNEL_ID_CH1) | \
XVPHY_TXRX_INIT_PLLGTRESET_MASK(XVPHY_CHANNEL_ID_CH2) | \
XVPHY_TXRX_INIT_PLLGTRESET_MASK(XVPHY_CHANNEL_ID_CH3) | \
XVPHY_TXRX_INIT_PLLGTRESET_MASK(XVPHY_CHANNEL_ID_CH4))
XVPHY_TXRX_INIT_PLLGTRESET_MASK
#define XVPHY_TXRX_INIT_PLLGTRESET_MASK(Ch)
PLL GT reset mask for channel.
Definition: xvphy_hw.h:337

PLL GT reset mask for all channels.

Referenced by XVphy_ResetGtPll().

#define XVPHY_TXRX_INIT_PLLGTRESET_MASK (   Ch)    (0x80 << (8 * (Ch - 1)))

PLL GT reset mask for channel.

Referenced by XVphy_ResetGtPll().

#define XVPHY_TXRX_INIT_PMARESET_MASK (   Ch)    (0x02 << (8 * (Ch - 1)))

PMA reset mask for channel.

#define XVPHY_TXRX_INIT_STATUS_PMARESETDONE_ALL_MASK
Value:
(XVPHY_TXRX_INIT_STATUS_PMARESETDONE_MASK(XVPHY_CHANNEL_ID_CH1) | \
XVPHY_TXRX_INIT_STATUS_PMARESETDONE_MASK(XVPHY_CHANNEL_ID_CH2) | \
XVPHY_TXRX_INIT_STATUS_PMARESETDONE_MASK(XVPHY_CHANNEL_ID_CH3) | \
XVPHY_TXRX_INIT_STATUS_PMARESETDONE_MASK(XVPHY_CHANNEL_ID_CH4))
XVPHY_TXRX_INIT_STATUS_PMARESETDONE_MASK
#define XVPHY_TXRX_INIT_STATUS_PMARESETDONE_MASK(Ch)
PMA reset done mask for channel.
Definition: xvphy_hw.h:372

PMA reset done mask for all channels.

#define XVPHY_TXRX_INIT_STATUS_PMARESETDONE_MASK (   Ch)    (0x02 << (8 * (Ch - 1)))

PMA reset done mask for channel.

#define XVPHY_TXRX_INIT_STATUS_POWERGOOD_MASK (   Ch)    (0x04 << (8 * (Ch - 1)))

Power good mask for channel.

#define XVPHY_TXRX_INIT_STATUS_RESETDONE_ALL_MASK
Value:
(XVPHY_TXRX_INIT_STATUS_RESETDONE_MASK(XVPHY_CHANNEL_ID_CH1) | \
XVPHY_TXRX_INIT_STATUS_RESETDONE_MASK(XVPHY_CHANNEL_ID_CH2) | \
XVPHY_TXRX_INIT_STATUS_RESETDONE_MASK(XVPHY_CHANNEL_ID_CH3) | \
XVPHY_TXRX_INIT_STATUS_RESETDONE_MASK(XVPHY_CHANNEL_ID_CH4))
XVPHY_TXRX_INIT_STATUS_RESETDONE_MASK
#define XVPHY_TXRX_INIT_STATUS_RESETDONE_MASK(Ch)
Reset done mask for channel.
Definition: xvphy_hw.h:369

Reset done mask for all channels.

#define XVPHY_TXRX_INIT_STATUS_RESETDONE_MASK (   Ch)    (0x01 << (8 * (Ch - 1)))

Reset done mask for channel.

#define XVPHY_VERSION_CORE_PATCH_MASK   0x00000F00

Core patch details.

#define XVPHY_VERSION_CORE_PATCH_SHIFT   8

Shift bits for core patch details.

#define XVPHY_VERSION_CORE_VER_MJR_MASK   0xFF000000

Core major version.

#define XVPHY_VERSION_CORE_VER_MJR_SHIFT   24

Shift bits for core major version.

#define XVPHY_VERSION_CORE_VER_MNR_MASK   0x00FF0000

Core minor version.

#define XVPHY_VERSION_CORE_VER_MNR_SHIFT   16

Shift bits for core minor version.

#define XVPHY_VERSION_CORE_VER_REV_MASK   0x0000F000

Core version revision.

#define XVPHY_VERSION_CORE_VER_REV_SHIFT   12

Shift bits for core version revision.

#define XVPHY_VERSION_INTER_REV_MASK   0x000000FF

Internal revision.

#define XVPHY_VERSION_REG   0x000

Version register offset.

Referenced by XVphy_GetVersion().

Enumeration Type Documentation

enum XVphy_ErrType

This typedef enumerates the possible error conditions.

Enumerator
XVPHY_ERR_QPLL_CFG 

QPLL CFG not found.

XVPHY_ERR_CPLL_CFG 

CPLL CFG not found.

XVPHY_ERR_NO_DRU 

No DRU in design.

XVPHY_ERR_VD_NOT_SPRTD 

Video Not Supported.

XVPHY_ERR_MMCM_CFG 

MMCM CFG not found.

XVPHY_ERR_PLL_LAYOUT 

PLL Error.

XVPHY_ERR_BONDED_DRU 

DRU and Bonded Mode Error.

XVPHY_ERR_NO_QPLL 

No QPLL Error.

XVPHY_ERR_DRU_CLK 

Wrong DRU clk freq Error.

XVPHY_ERR_USRCLK 

USRCLK Error.

enum XVphy_HdmiTx_Patgen

This typedef enumerates the Linerate to TMDS Clock ratio for HDMI TX TMDS Clock pattern generator.

Enumerator
XVPHY_Patgen_Ratio_10 

LR:Clock Ratio = 10.

XVPHY_Patgen_Ratio_20 

LR:Clock Ratio = 20.

XVPHY_Patgen_Ratio_30 

LR:Clock Ratio = 30.

XVPHY_Patgen_Ratio_40 

LR:Clock Ratio = 40.

XVPHY_Patgen_Ratio_50 

LR:Clock Ratio = 50.

enum XVphy_LogEvent

This typedef enumerates the Video PHY log events.

Enumerator
XVPHY_LOG_EVT_NONE 

Log event none.

XVPHY_LOG_EVT_QPLL_EN 

Log event QPLL enable.

XVPHY_LOG_EVT_QPLL_RST 

Log event QPLL reset.

XVPHY_LOG_EVT_QPLL_LOCK 

Log event QPLL lock.

XVPHY_LOG_EVT_QPLL_RECONFIG 

Log event QPLL reconfig.

XVPHY_LOG_EVT_QPLL0_EN 

Log event QPLL0 enable.

XVPHY_LOG_EVT_QPLL0_RST 

Log event QPLL0 reset.

XVPHY_LOG_EVT_QPLL0_LOCK 

Log event QPLL0 lock.

XVPHY_LOG_EVT_QPLL0_RECONFIG 

Log event QPLL0 reconfig.

XVPHY_LOG_EVT_QPLL1_EN 

Log event QPLL1 enable.

XVPHY_LOG_EVT_QPLL1_RST 

Log event QPLL1 reset.

XVPHY_LOG_EVT_QPLL1_LOCK 

Log event QPLL1 lock.

XVPHY_LOG_EVT_QPLL1_RECONFIG 

Log event QPLL1 reconfig.

XVPHY_LOG_EVT_PLL0_EN 

Log event PLL0 reset.

XVPHY_LOG_EVT_PLL0_RST 

Log event PLL0 reset.

XVPHY_LOG_EVT_PLL0_LOCK 

Log event PLL0 lock.

XVPHY_LOG_EVT_PLL0_RECONFIG 

Log event PLL0 reconfig.

XVPHY_LOG_EVT_PLL1_EN 

Log event PLL1 reset.

XVPHY_LOG_EVT_PLL1_RST 

Log event PLL1 reset.

XVPHY_LOG_EVT_PLL1_LOCK 

Log event PLL1 lock.

XVPHY_LOG_EVT_PLL1_RECONFIG 

Log event PLL1 reconfig.

XVPHY_LOG_EVT_CPLL_EN 

Log event CPLL reset.

XVPHY_LOG_EVT_CPLL_RST 

Log event CPLL reset.

XVPHY_LOG_EVT_CPLL_LOCK 

Log event CPLL lock.

XVPHY_LOG_EVT_CPLL_RECONFIG 

Log event CPLL reconfig.

XVPHY_LOG_EVT_TXPLL_EN 

Log event TXPLL enable.

XVPHY_LOG_EVT_TXPLL_RST 

Log event TXPLL reset.

XVPHY_LOG_EVT_RXPLL_EN 

Log event RXPLL enable.

XVPHY_LOG_EVT_RXPLL_RST 

Log event RXPLL reset.

XVPHY_LOG_EVT_GTRX_RST 

Log event GT RX reset.

XVPHY_LOG_EVT_GTTX_RST 

Log event GT TX reset.

XVPHY_LOG_EVT_VID_TX_RST 

Log event Vid TX reset.

XVPHY_LOG_EVT_VID_RX_RST 

Log event Vid RX reset.

XVPHY_LOG_EVT_TX_ALIGN 

Log event TX align.

XVPHY_LOG_EVT_TX_ALIGN_TMOUT 

Log event TX align Timeout.

XVPHY_LOG_EVT_TX_TMR 

Log event TX timer.

XVPHY_LOG_EVT_RX_TMR 

Log event RX timer.

XVPHY_LOG_EVT_GT_RECONFIG 

Log event GT reconfig.

XVPHY_LOG_EVT_GT_TX_RECONFIG 

Log event GT reconfig.

XVPHY_LOG_EVT_GT_RX_RECONFIG 

Log event GT reconfig.

XVPHY_LOG_EVT_INIT 

Log event init.

XVPHY_LOG_EVT_TXPLL_RECONFIG 

Log event TXPLL reconfig.

XVPHY_LOG_EVT_RXPLL_RECONFIG 

Log event RXPLL reconfig.

XVPHY_LOG_EVT_RXPLL_LOCK 

Log event RXPLL lock.

XVPHY_LOG_EVT_TXPLL_LOCK 

Log event TXPLL lock.

XVPHY_LOG_EVT_TX_RST_DONE 

Log event TX reset done.

XVPHY_LOG_EVT_RX_RST_DONE 

Log event RX reset done.

XVPHY_LOG_EVT_TX_FREQ 

Log event TX frequency.

XVPHY_LOG_EVT_RX_FREQ 

Log event RX frequency.

XVPHY_LOG_EVT_DRU_EN 

Log event DRU enable/disable.

XVPHY_LOG_EVT_GT_PLL_LAYOUT 

Log event GT PLL Layout Change.

XVPHY_LOG_EVT_GT_UNBONDED 

Log event GT Unbonded Change.

XVPHY_LOG_EVT_1PPC_ERR 

Log event 1 PPC Error.

XVPHY_LOG_EVT_PPC_MSMTCH_ERR 

Log event PPC MismatchError.

XVPHY_LOG_EVT_VDCLK_HIGH_ERR 

Log event VidClk more than 148.5 MHz.

XVPHY_LOG_EVT_NO_DRU 

Log event Vid not supported no DRU.

XVPHY_LOG_EVT_GT_QPLL_CFG_ERR 

Log event QPLL Config not found.

XVPHY_LOG_EVT_GT_CPLL_CFG_ERR 

Log event QPLL Config not found.

XVPHY_LOG_EVT_VD_NOT_SPRTD_ERR 

Log event Vid format not supported.

XVPHY_LOG_EVT_MMCM_ERR 

Log event MMCM Config not found.

XVPHY_LOG_EVT_HDMI20_ERR 

Log event HDMI2.0 not supported.

XVPHY_LOG_EVT_NO_QPLL_ERR 

Log event QPLL not present.

XVPHY_LOG_EVT_DRU_CLK_ERR 

Log event DRU clk wrong freq.

XVPHY_LOG_EVT_USRCLK_ERR 

Log event usrclk more than 297 MHz.

XVPHY_LOG_EVT_DUMMY 

Dummy Event should be last.