vphy Documentation

This is main header file of the Xilinx Video PHY Controller driverVideo PHY Controller Overview

The PHY is intended to simplify the use of serial transceivers and adds domain-specific configurability. The Video PHY Controller IP is not intended to be used as a stand alone IP and must be used with Xilinx Video MACs such as HDMI 1.4/2.0 Transmitter/Receiver Subsystems and DisplayPort TX/RX Subsystems. The core enables simpler connectivity between MAC layers for TX and RX paths. However, it is still important to understand the behavior, usage, and any limitations of the transceivers. See the device specific transceiver user guide for details.

Video PHY Controller Driver Features

Video PHY Controller driver supports following features

• Xilinx DisplayPort and HDMI MAC IPs
• GTXE2, GTPE2, GTHE2, GTHE3, GTHE4 and GTYE4 GT types
• HDMI:
• 2 or 4 pixel-wide video interface
• 8/10/12/16 bits per component
• RGB & YCbCr color space
• Up to 4k2k 60Hz resolution at both Input and Output interface

MODIFICATION HISTORY:

Ver   Who  Date     Changes



1.0   als  10/19/15 Initial release.
1.1   gm   02/01/16 Added EAST, WEST, PLL0 and PLL1 definitions
                    for GTPE2.
                    Added more events to XVphy_LogEvent definitions
                    Added TxBufferBypass in XVphy_Config structure
                    Added XVphy_SetDefaultPpc and XVphy_SetPpc functions
      als           Added XVphy_GetLineRateHz function.
1.2   gm            Added HdmiFastSwitch in XVphy_Config
                    Changed EffectiveAddr datatype in XVphy_CfgInitialize
                      to UINTPTR
                    Added log events for debugging
1.2   gm   11/11/19 Added TransceiverWidth in XVphy_Config
1.4   gm   29/11/16 Moved internally used APIs to xvphy_i.c/h
                    Added preprocessor directives for sw footprint reduction
                    Made debug log optional (can be disabled via makefile)
                    Added ERR_IRQ type_defs (not for official use for
                      Xilinx debugging)
                    Added transceiver width, AXIlite clk frequency and
                      err_irq in XVphy_Config
1.5   gm   08/05/17 Added DrpClkFreq in XVphy_Config
1.6   gm   06/08/17 Added XVPHY_LOG_EVT_HDMI20_ERR &
                      XVPHY_LOG_EVT_DRU_CLK_ERR XVphy_LogEvent enum
                    Added intr events for TX and RX MMCM lock
                    Marked XVphy_DrpWrite and XVphy_DrpRead as deprecated
                    Added XVphy_SetErrorCallback API
                    Changed ClkOutxDiv declaration to u16
                    Marked XVphy_HdmiInitialize deprecated and replaced by
                       XVphy_Hdmi_CfgInitialize
1.7   gm   13/09/17 Added GTYE4 support
                    Added XVphy_SetPolarity, XVphy_SetPrbsSel and
                       XVphy_TxPrbsForceError APIs
1.8   gm   05/14/18 Updated CDR values for DP in xvphy_gtye4.c
                    Removed XVphy_DrpWrite and XVphy_DrpRead APIs
           23/07/18 Added APIs XVphy_SetTxVoltageSwing and
                      XVphy_SetTxPreEmphasis from xvphy_i.c/h
                    Added XVphy_SetTxPostCursor API
1.9   gm   14/05/18 Added XVphy_SetRxLpm from xvphy_i.c/.h
                    Removed deprecated XVphy_HdmiInitialize API