Overview

Contains a minimal set of functions for the XVphy driver that allow access to all of the Video PHY core's functionality.

See xvphy.h for a detailed description of the driver.

Note: None.

MODIFICATION HISTORY:

Ver   Who  Date     Changes



1.0   als  19/10/15 Initial release.
1.1   gm   18/03/16 Added XVphy_Gthe3RxPllRefClkDiv1Reconfig function
1.2   gm   26/08/16 Suppressed warning messages due to unused arguments
1.4   gm   29/11/16 Added preprocessor directives for sw footprint reduction
                    Changed TX reconfig hook from TxPllRefClkDiv1Reconfig to
                      TxChReconfig
                    Added TX datawidth dynamic reconfiguration
                    Added N2=8 divider for CPLL for DP
                    Added CPLL_CFGx reconfiguration in
                      XVphy_Gthe3ClkChReconfig API
                    Corrected the default return value of DRP encoding
                      APIs to prevent overwritting the reserved bits
1.6   gm   12/06/17 Changed XVphy_DrpRead with XVphy_DrpRd
                    Changed XVphy_DrpWrite with XVphy_DrpWr
                    Improved status return of APIs with DRP Rd and Wr
                    Added N2=8 divider for CPLL for HDMI
1.7   gm   13/09/17 Disabled intelligent clock sel in QPLL0/1 configuration
                    Updated DP CDR config for 8.1 Gbps
                    Updated XVPHY_QPLL0_MAX to 16375000000LL
1.8   gm   05/09/18 Enable IPS only when XVphy_GetRefClkSourcesCount
                      returns more than 1.