dphy
Xilinx SDK Drivers API Documentation
dphy Documentation

This file contains the implementation of the MIPI DPHY Controller driver.User documentation for the driver functions is contained in this file in the form of comment blocks at the front of each function.

MIPI DPHY Overview

The DPHY currently supports the MIPI?Alliance Specification for DPHY Version 1.1.

It is capable of synchronous transfer at high speed mode at 80-1500 Mbps It has one clock lane and up to 4 data lanes. These lanes are unidirectional. It can do asynchronous transfer at upto 10 Mbps in low power mode. The clock lane can be in low power mode or high speed mode whereas the data lanes can be in Low power, High power or Escape mode.

The programmable parameters like IDelay, Wakeup, HS Timeout, Esc Timeout are present and various status like Stop state, Error detected, ULPS state,etc are available through the status register

Core Features

The GUI in IPI allows for the following configurations

  • Lanes ( 1 to 4 )
  • Line Rate (80 - 1500 Mbps)
  • Data Flow direction (Tx or Rx)
  • Escape Clock (10 - 20 Mhz)
  • LPX period (50 - 100 ns)
  • Enable register interface
  • HS Timeout in Bytes (1000 - 65541)
  • Escape Timeout in ns (800 - 25600)

Software Initialization & Configuration

By default, the DPHY core is initialized and ready.

The application needs to do following steps in order for preparing the MIPI DPHY core to be ready.

  • Call XDphy_LookupConfig using a device ID to find the core configuration.
  • Call XDphy_CfgInitialize to initialize the device and the driver instance associated with it.
  • Individual parameters can be configured by sending values with appropriate handles.

Interrupts

There are no interrupts from the DPHY.

Virtual Memory

This driver supports Virtual Memory. The RTOS is responsible for calculating the correct device base address in Virtual Memory space.

Threads

This driver is not thread safe. Any needs for threads or thread mutual exclusion must be satisfied by the layer above this driver.

Asserts

Asserts are used within all Xilinx drivers to enforce constraints on argument values. Asserts can be turned off on a system-wide basis by defining, at compile time, the NDEBUG identifier. By default, asserts are turned on and it is recommended that application developers leave asserts on during development.

Building the driver

The DPHY driver is composed of source files and doesn't depend on any other drivers.

MODIFICATION HISTORY:
Ver Who Date     Changes


1.0 vsa 07/08/15 Initial release 1.1 sss 08/17/16 Added 64 bit support ms 01/23/17 Modified xil_printf statement in main function for all examples to ensure that "Successfully ran" and "Failed" strings are available in all examples. This is a fix for CR-965028. 1.2 vsa 03/02/17 Add support for HS_SETTLE register ms 03/17/17 Added readme.txt file in examples folder for doxygen generation. ms 04/05/17 Modified Comment lines in functions of dphy examples to recognize it as documentation block for doxygen generation of examples.