Overview

This example demonstrates how to use the AXI Video DMA in loopback mode to do video frame transfers.

This example reads video frames from memory, using Memory Map to Stream (MM2S) interface, and then video frames are written to memory using Stream to Memory Map (S2MM) AXI4 interface. At the end of transfer it does sanity check and report pass/fail status.

To see the debug print, you need a Uart16550 or uartlite in your system, and please set "-DDEBUG" in your compiler options. You need to rebuild your software executable.

Note: The values of DDR_BASE_ADDR and DDR_HIGH_ADDR should be as per the HW system.

MODIFICATION HISTORY:

Ver   Who  Date     Changes
----- ---- -------- -------------------------------------------------------
1.00a jz   07/26/10 First release
1.01a jz   09/26/10 Updated callback function signature
2.00a jz   12/10/10 Added support for direct register access mode, v3 core
2.01a rvp  01/22/11 Renamed the example file to be consistent
                       Added support to the example to use SCU GIC interrupt
               controller for ARM, some functions in this example have
               changed.
      rkv  03/28/11 Updated to support for frame store register.
3.00a srt  08/26/11 Added support for Flush on Frame Sync Feature.
4.00a srt  03/06/12 Modified interrupt support for Zynq.
4.02a srt  09/25/12 Fixed CR 677704
               Description - Arguments misused in function
                    XAxiVdma_IntrEnable().
4.03a srt  03/01/13 Updated DDR base address for IPI designs (CR 703656).
6.2   ms   01/23/17 Modified xil_printf statement in main function to
                    ensure that "Successfully ran" and "Failed" strings
                    are available in all examples. This is a fix for
                    CR-965028.
6.5   rsp  12/01/17 Set TX/RX framebuffer count to IP default. CR-990409
6.6   rsp  07/02/18 Set Vertical Flip state to IP default. CR-989453
6.7   sk   05/06/20 Fix optimization level 2 failure in release mode.
6.8   sk   07/07/20 Add frame data check support
6.9      sk   05/25/21 Modify the ReadSetup buffer initialization call and
               CheckFrame to correct the example logic.
6.9      sk   05/25/21 Fix data comparison failure wtih optimization level 2.
6.10  rsp  09/09/21 Fix read/write done count check in while loop.
                    Remove unused variable GCC warning in ReadSetup().
6.11  rsp  03/16/21 After Wr/Rd channel reset ensure it's completed
                    and then do data comparison.
6.12  sa   08/12/22 Updated the example to use latest MIG cannoical define
                       i.e XPAR_MIG_0_C0_DDR4_MEMORY_MAP_BASEADDR.
6.13     sa   09/29/22 Fix infinite loops in the example.

Functions
int	main (void)
	Main function. More...

Function Documentation

int main ( void )

Main function.

This function is the main entry point of the example on DMA core. It sets up DMA engine to be ready to receive and send frames, and start the transfers. It waits for the transfer of the specified number of frame sets, and check for transfer errors.

Returns

XST_SUCCESS if example finishes successfully
XST_FAILURE if example fails.

Note: None.

References XAxiVdma_Config::BaseAddress, XAxiVdma_Config::IntrParent, XAxiVdma_Config::MaxFrameStoreNum, XAxiVdma_FrameCounter::ReadDelayTimerCount, XAxiVdma_FrameCounter::ReadFrameCount, XAxiVdma_FrameCounter::WriteDelayTimerCount, XAxiVdma_FrameCounter::WriteFrameCount, XAxiVdma_CfgInitialize(), XAxiVdma_GetStatus(), XAXIVDMA_HANDLER_ERROR, XAXIVDMA_HANDLER_GENERAL, XAxiVdma_IntrEnable(), XAXIVDMA_IXR_ALL_MASK, XAxiVdma_LookupConfig(), XAXIVDMA_READ, XAxiVdma_ReadIntrHandler(), XAxiVdma_Reset(), XAxiVdma_ResetNotDone(), XAxiVdma_SetCallBack(), XAxiVdma_SetFrameCounter(), XAxiVdma_SetFrmStore(), XAXIVDMA_WRITE, and XAxiVdma_WriteIntrHandler().

Overview

Functions

Function Documentation