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#define | XVIDC_EDID_HEADER 0x00 |
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#define | XVIDC_EDID_VPI_ID_MAN_NAME0 0x08 |
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#define | XVIDC_EDID_VPI_ID_MAN_NAME1 0x09 |
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#define | XVIDC_EDID_VPI_ID_PROD_CODE_LSB 0x0A |
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#define | XVIDC_EDID_VPI_ID_PROD_CODE_MSB 0x0B |
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#define | XVIDC_EDID_VPI_ID_SN0 0x0C |
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#define | XVIDC_EDID_VPI_ID_SN1 0x0D |
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#define | XVIDC_EDID_VPI_ID_SN2 0x0E |
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#define | XVIDC_EDID_VPI_ID_SN3 0x0F |
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#define | XVIDC_EDID_VPI_WEEK_MAN 0x10 |
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#define | XVIDC_EDID_VPI_YEAR 0x11 |
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#define | XVIDC_EDID_STRUCT_VER 0x12 |
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#define | XVIDC_EDID_STRUCT_REV 0x13 |
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#define | XVIDC_EDID_BDISP_VID 0x14 |
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#define | XVIDC_EDID_BDISP_H_SSAR 0x15 |
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#define | XVIDC_EDID_BDISP_V_SSAR 0x16 |
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#define | XVIDC_EDID_BDISP_GAMMA 0x17 |
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#define | XVIDC_EDID_BDISP_FEATURE 0x18 |
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#define | XVIDC_EDID_CC_RG_LOW 0x19 |
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#define | XVIDC_EDID_CC_BW_LOW 0x1A |
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#define | XVIDC_EDID_CC_REDX_HIGH 0x1B |
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#define | XVIDC_EDID_CC_REDY_HIGH 0x1C |
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#define | XVIDC_EDID_CC_GREENX_HIGH 0x1D |
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#define | XVIDC_EDID_EST_TIMINGS_I 0x23 |
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#define | XVIDC_EDID_EST_TIMINGS_II 0x24 |
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#define | XVIDC_EDID_EST_TIMINGS_MAN 0x25 |
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#define | XVIDC_EDID_STD_TIMINGS_H(N) (0x26 + 2 * (N - 1)) |
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#define | XVIDC_EDID_STD_TIMINGS_AR_FRR(N) (0x27 + 2 * (N - 1)) |
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#define | XVIDC_EDID_18BYTE_DESCRIPTOR(N) (0x36 + 18 * (N - 1)) |
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#define | XVIDC_EDID_PTM (XVIDC_EDID_18BYTE_DESCRIPTOR(1)) |
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#define | XVIDC_EDID_DTD_PTM_PIXEL_CLK_KHZ_LSB 0x00 |
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#define | XVIDC_EDID_DTD_PTM_PIXEL_CLK_KHZ_MSB 0x01 |
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#define | XVIDC_EDID_DTD_PTM_HRES_LSB 0x02 |
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#define | XVIDC_EDID_DTD_PTM_HBLANK_LSB 0x03 |
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#define | XVIDC_EDID_DTD_PTM_HRES_HBLANK_U4 0x04 |
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#define | XVIDC_EDID_DTD_PTM_VRES_LSB 0x05 |
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#define | XVIDC_EDID_DTD_PTM_VBLANK_LSB 0x06 |
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#define | XVIDC_EDID_DTD_PTM_VRES_VBLANK_U4 0x07 |
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#define | XVIDC_EDID_DTD_PTM_HFPORCH_LSB 0x08 |
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#define | XVIDC_EDID_DTD_PTM_HSPW_LSB 0x09 |
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#define | XVIDC_EDID_DTD_PTM_VFPORCH_VSPW_L4 0x0A |
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#define | XVIDC_EDID_DTD_PTM_XFPORCH_XSPW_U2 0x0B |
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#define | XVIDC_EDID_DTD_PTM_HIMGSIZE_MM_LSB 0x0C |
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#define | XVIDC_EDID_DTD_PTM_VIMGSIZE_MM_LSB 0x0D |
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#define | XVIDC_EDID_DTD_PTM_XIMGSIZE_MM_U4 0x0E |
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#define | XVIDC_EDID_DTD_PTM_HBORDER 0x0F |
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#define | XVIDC_EDID_DTD_PTM_VBORDER 0x10 |
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#define | XVIDC_EDID_DTD_PTM_SIGNAL 0x11 |
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#define | XVIDC_EDID_EXT_BLK_COUNT 0x7E |
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#define | XVIDC_EDID_CHECKSUM 0x7F |
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#define | XVIDC_EDID_CC_GREENY_HIGH 0x1E |
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#define | XVIDC_EDID_CC_BLUEX_HIGH 0x1F |
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#define | XVIDC_EDID_CC_BLUEY_HIGH 0x20 |
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#define | XVIDC_EDID_CC_WHITEX_HIGH 0x21 |
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#define | XVIDC_EDID_CC_WHITEY_HIGH 0x22 |
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#define | XVIDC_EDID_VPI_ID_MAN_NAME0_CHAR0_SHIFT 2 |
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#define | XVIDC_EDID_VPI_ID_MAN_NAME0_CHAR0_MASK (0x1F << 2) |
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#define | XVIDC_EDID_VPI_ID_MAN_NAME0_CHAR1_MASK 0x03 |
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#define | XVIDC_EDID_VPI_ID_MAN_NAME0_CHAR1_POS 3 |
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#define | XVIDC_EDID_VPI_ID_MAN_NAME1_CHAR1_SHIFT 5 |
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#define | XVIDC_EDID_VPI_ID_MAN_NAME1_CHAR2_MASK 0x1F |
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#define | XVIDC_EDID_BDISP_VID_VSI_SHIFT 7 |
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#define | XVIDC_EDID_BDISP_VID_VSI_MASK (0x01 << 7) |
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#define | XVIDC_EDID_BDISP_VID_ANA_SLS_SHIFT 5 |
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#define | XVIDC_EDID_BDISP_VID_ANA_SLS_MASK (0x03 << 5) |
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#define | XVIDC_EDID_BDISP_VID_ANA_SLS_0700_0300_1000 0x0 |
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#define | XVIDC_EDID_BDISP_VID_ANA_SLS_0714_0286_1000 0x1 |
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#define | XVIDC_EDID_BDISP_VID_ANA_SLS_1000_0400_1400 0x2 |
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#define | XVIDC_EDID_BDISP_VID_ANA_SLS_0700_0000_0700 0x3 |
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#define | XVIDC_EDID_BDISP_VID_ANA_VID_SETUP_MASK (0x01 << 4) |
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#define | XVIDC_EDID_BDISP_VID_ANA_SEP_SYNC_HV_MASK (0x01 << 3) |
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#define | XVIDC_EDID_BDISP_VID_ANA_COMP_SYNC_H_MASK (0x01 << 2) |
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#define | XVIDC_EDID_BDISP_VID_ANA_COMP_SYNC_G_MASK (0x01 << 1) |
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#define | XVIDC_EDID_BDISP_VID_ANA_SERR_V_SYNC_MASK (0x01) |
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#define | XVIDC_EDID_BDISP_VID_DIG_BPC_SHIFT 4 |
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#define | XVIDC_EDID_BDISP_VID_DIG_BPC_MASK (0x7 << 4) |
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#define | XVIDC_EDID_BDISP_VID_DIG_BPC_UNDEF 0x0 |
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#define | XVIDC_EDID_BDISP_VID_DIG_BPC_6 0x1 |
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#define | XVIDC_EDID_BDISP_VID_DIG_BPC_8 0x2 |
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#define | XVIDC_EDID_BDISP_VID_DIG_BPC_10 0x3 |
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#define | XVIDC_EDID_BDISP_VID_DIG_BPC_12 0x4 |
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#define | XVIDC_EDID_BDISP_VID_DIG_BPC_14 0x5 |
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#define | XVIDC_EDID_BDISP_VID_DIG_BPC_16 0x6 |
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#define | XVIDC_EDID_BDISP_VID_DIG_VIS_MASK 0xF |
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#define | XVIDC_EDID_BDISP_VID_DIG_VIS_UNDEF 0x0 |
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#define | XVIDC_EDID_BDISP_VID_DIG_VIS_DVI 0x1 |
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#define | XVIDC_EDID_BDISP_VID_DIG_VIS_HDMIA 0x2 |
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#define | XVIDC_EDID_BDISP_VID_DIG_VIS_HDMIB 0x3 |
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#define | XVIDC_EDID_BDISP_VID_DIG_VIS_MDDI 0x4 |
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#define | XVIDC_EDID_BDISP_VID_DIG_VIS_DP 0x5 |
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#define | XVIDC_EDID_BDISP_FEATURE_PM_STANDBY_MASK (0x1 << 7) |
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#define | XVIDC_EDID_BDISP_FEATURE_PM_SUSPEND_MASK (0x1 << 6) |
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#define | XVIDC_EDID_BDISP_FEATURE_PM_OFF_VLP_MASK (0x1 << 5) |
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#define | XVIDC_EDID_BDISP_FEATURE_ANA_COLORTYPE_SHIFT 3 |
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#define | XVIDC_EDID_BDISP_FEATURE_ANA_COLORTYPE_MASK (0x3 << 3) |
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#define | XVIDC_EDID_BDISP_FEATURE_ANA_COLORTYPE_MCG 0x0 |
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#define | XVIDC_EDID_BDISP_FEATURE_ANA_COLORTYPE_RGB 0x1 |
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#define | XVIDC_EDID_BDISP_FEATURE_ANA_COLORTYPE_NRGB 0x2 |
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#define | XVIDC_EDID_BDISP_FEATURE_ANA_COLORTYPE_UNDEF 0x3 |
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#define | XVIDC_EDID_BDISP_FEATURE_DIG_COLORENC_YCRCB444_MASK (0x1 << 3) |
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#define | XVIDC_EDID_BDISP_FEATURE_DIG_COLORENC_YCRCB422_MASK (0x1 << 4) |
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#define | XVIDC_EDID_BDISP_FEATURE_SRGB_DEF_MASK (0x1 << 2) |
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#define | XVIDC_EDID_BDISP_FEATURE_PTM_INC_MASK (0x1 << 1) |
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#define | XVIDC_EDID_BDISP_FEATURE_CONTFREQ_MASK (0x1) |
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#define | XVIDC_EDID_CC_HIGH_SHIFT 2 |
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#define | XVIDC_EDID_CC_RBX_LOW_SHIFT 6 |
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#define | XVIDC_EDID_CC_RBY_LOW_SHIFT 4 |
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#define | XVIDC_EDID_CC_RBY_LOW_MASK (0x3 << 4) |
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#define | XVIDC_EDID_CC_GWX_LOW_SHIFT 2 |
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#define | XVIDC_EDID_CC_GWX_LOW_MASK (0x3 << 2) |
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#define | XVIDC_EDID_CC_GWY_LOW_MASK (0x3) |
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#define | XVIDC_EDID_CC_GREENY_HIGH 0x1E |
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#define | XVIDC_EDID_CC_BLUEX_HIGH 0x1F |
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#define | XVIDC_EDID_CC_BLUEY_HIGH 0x20 |
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#define | XVIDC_EDID_CC_WHITEX_HIGH 0x21 |
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#define | XVIDC_EDID_CC_WHITEY_HIGH 0x22 |
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#define | XVIDC_EDID_EST_TIMINGS_I_720x400_70_MASK (0x1 << 7) |
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#define | XVIDC_EDID_EST_TIMINGS_I_720x400_88_MASK (0x1 << 6) |
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#define | XVIDC_EDID_EST_TIMINGS_I_640x480_60_MASK (0x1 << 5) |
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#define | XVIDC_EDID_EST_TIMINGS_I_640x480_67_MASK (0x1 << 4) |
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#define | XVIDC_EDID_EST_TIMINGS_I_640x480_72_MASK (0x1 << 3) |
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#define | XVIDC_EDID_EST_TIMINGS_I_640x480_75_MASK (0x1 << 2) |
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#define | XVIDC_EDID_EST_TIMINGS_I_800x600_56_MASK (0x1 << 1) |
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#define | XVIDC_EDID_EST_TIMINGS_I_800x600_60_MASK (0x1) |
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#define | XVIDC_EDID_EST_TIMINGS_II_800x600_72_MASK (0x1 << 7) |
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#define | XVIDC_EDID_EST_TIMINGS_II_800x600_75_MASK (0x1 << 6) |
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#define | XVIDC_EDID_EST_TIMINGS_II_832x624_75_MASK (0x1 << 5) |
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#define | XVIDC_EDID_EST_TIMINGS_II_1024x768_87_MASK (0x1 << 4) |
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#define | XVIDC_EDID_EST_TIMINGS_II_1024x768_60_MASK (0x1 << 3) |
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#define | XVIDC_EDID_EST_TIMINGS_II_1024x768_70_MASK (0x1 << 2) |
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#define | XVIDC_EDID_EST_TIMINGS_II_1024x768_75_MASK (0x1 << 1) |
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#define | XVIDC_EDID_EST_TIMINGS_II_1280x1024_75_MASK (0x1) |
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#define | XVIDC_EDID_EST_TIMINGS_MAN_1152x870_75_MASK (0x1 << 7) |
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#define | XVIDC_EDID_EST_TIMINGS_MAN_MASK (0x7F) |
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#define | XVIDC_EDID_STD_TIMINGS_AR_SHIFT 6 |
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#define | XVIDC_EDID_STD_TIMINGS_AR_16_10 0x0 |
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#define | XVIDC_EDID_STD_TIMINGS_AR_4_3 0x1 |
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#define | XVIDC_EDID_STD_TIMINGS_AR_5_4 0x2 |
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#define | XVIDC_EDID_STD_TIMINGS_AR_16_9 0x3 |
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#define | XVIDC_EDID_STD_TIMINGS_FRR_MASK (0x3F) |
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#define | XVIDC_EDID_DTD_PTM_XRES_XBLANK_U4_XBLANK_MASK 0x0F |
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#define | XVIDC_EDID_DTD_PTM_XRES_XBLANK_U4_XRES_MASK 0xF0 |
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#define | XVIDC_EDID_DTD_PTM_XRES_XBLANK_U4_XRES_SHIFT 4 |
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#define | XVIDC_EDID_DTD_PTM_VFPORCH_VSPW_L4_VSPW_MASK 0x0F |
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#define | XVIDC_EDID_DTD_PTM_VFPORCH_VSPW_L4_VFPORCH_MASK 0xF0 |
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#define | XVIDC_EDID_DTD_PTM_VFPORCH_VSPW_L4_VFPORCH_SHIFT 4 |
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#define | XVIDC_EDID_DTD_PTM_XFPORCH_XSPW_U2_HFPORCH_MASK 0xC0 |
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#define | XVIDC_EDID_DTD_PTM_XFPORCH_XSPW_U2_HSPW_MASK 0x30 |
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#define | XVIDC_EDID_DTD_PTM_XFPORCH_XSPW_U2_VFPORCH_MASK 0x0C |
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#define | XVIDC_EDID_DTD_PTM_XFPORCH_XSPW_U2_VSPW_MASK 0x03 |
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#define | XVIDC_EDID_DTD_PTM_XFPORCH_XSPW_U2_HFPORCH_SHIFT 6 |
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#define | XVIDC_EDID_DTD_PTM_XFPORCH_XSPW_U2_HSPW_SHIFT 4 |
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#define | XVIDC_EDID_DTD_PTM_XFPORCH_XSPW_U2_VFPORCH_SHIFT 2 |
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#define | XVIDC_EDID_DTD_PTM_XIMGSIZE_MM_U4_VIMGSIZE_MM_MASK 0x0F |
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#define | XVIDC_EDID_DTD_PTM_XIMGSIZE_MM_U4_HIMGSIZE_MM_MASK 0xF0 |
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#define | XVIDC_EDID_DTD_PTM_XIMGSIZE_MM_U4_HIMGSIZE_MM_SHIFT 4 |
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#define | XVIDC_EDID_DTD_PTM_SIGNAL_INTERLACED_MASK 0x80 |
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#define | XVIDC_EDID_DTD_PTM_SIGNAL_INTERLACED_SHIFT 7 |
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#define | XVIDC_EDID_DTD_PTM_SIGNAL_HPOLARITY_MASK 0x02 |
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#define | XVIDC_EDID_DTD_PTM_SIGNAL_VPOLARITY_MASK 0x04 |
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#define | XVIDC_EDID_DTD_PTM_SIGNAL_HPOLARITY_SHIFT 1 |
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#define | XVIDC_EDID_DTD_PTM_SIGNAL_VPOLARITY_SHIFT 2 |
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