dp14txss
Xilinx Vitis Drivers API Documentation
xdptxss_hw.h File Reference

Macros

#define XDPTXSS_HW_H_
 Prevent circular inclusions by using protection macros.
 
#define XDPTXSS_LINK_BW_SET_162GBPS   XDP_TX_LINK_BW_SET_162GBPS
 1.62 Gbps link rate.
 
#define XDPTXSS_LINK_BW_SET_270GBPS   XDP_TX_LINK_BW_SET_270GBPS
 2.70 Gbps link rate.
 
#define XDPTXSS_LINK_BW_SET_540GBPS   XDP_TX_LINK_BW_SET_540GBPS
 5.40 Gbps link rate.
 
#define XDPTXSS_LINK_BW_SET_810GBPS   XDP_TX_LINK_BW_SET_810GBPS
 8.10 Gbps link rate.
 
#define XDPTXSS_LANE_COUNT_SET_1   XDP_TX_LANE_COUNT_SET_1
 Lane count of 1.
 
#define XDPTXSS_LANE_COUNT_SET_2   XDP_TX_LANE_COUNT_SET_2
 Lane count of 2.
 
#define XDPTXSS_LANE_COUNT_SET_4   XDP_TX_LANE_COUNT_SET_4
 Lane count of 4.
 
#define XDPTXSS_INTERRUPT_MASK   XDP_TX_INTERRUPT_MASK
 Masks the specified interrupt sources.
 
#define XDPTXSS_INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK   XDP_TX_INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK
 Mask HPD pulse detected interrupt.
 
#define XDPTXSS_INTERRUPT_MASK_HPD_EVENT_MASK   XDP_TX_INTERRUPT_MASK_HPD_EVENT_MASK
 Mask HPD event interrupt.
 
#define XDPTXSS_NUM_STREAMS   4
 Maximum number of streams supported.
 
Register access macro definition
#define XDpTxSs_In32   Xil_In32
 Input Operations.
 
#define XDpTxSs_Out32   Xil_Out32
 Output Operations.
 
#define XDpTxSs_ReadReg(BaseAddress, RegOffset)   XDpTxSs_In32((BaseAddress) + ((u32)RegOffset))
 This macro reads a value from a DisplayPort Transmitter Subsystem register.
 
#define XDpTxSs_WriteReg(BaseAddress, RegOffset, Data)   XDpTxSs_Out32((BaseAddress) + ((u32)RegOffset), (u32)(Data))
 This macro writes a value to a DisplayPort Transmitter Subsystem register.